As the density of semiconductor integrated circuits continues to increase and the corresponding size of circuit elements decreases, fabrication yields and device performance issues continue to arise. For instance, as pitch between metal fill vias and/or trenches in back end of line (BEOL) interconnect structures continues to decrease, metal fill issues are arising or becoming more significant due, in part, to higher desired aspect ratios of the structures. Further, as circuit size decreases, performance may be dominated by interconnect resistive-capacitive (RC) delay, for instance, between interconnect layers. Accordingly, enhanced interconnect and enhanced interlayer structures and fabrication methods are needed.